Conferences@CVEST

2016



2015



2014



2013



2012



2011



2010



2009



2008


  • Process Variation Aware Issue Queue Design, K Raghavendra,Madhu Mutyam, Design, automation and test in Europe (DATE 2008 2008), March 2008 :1438-1443 , Munich.

  • Reduced-order Modeling of High Speed VLSI Interconnects using Static Superelement Technique for Nano Meter Designs, R Ravindra J V ,M.B Srinivas, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008), June 2008 , Anaheim, CA, USA. (Co-located with the 45th Design Automation Conference (DAC 2008)).

  • Static Superelement Technique based Model Order Reduction for High Speed Nanometer Designs, R Ravindra J V ,M.B Srinivas, The 8th International Conference on Nanotechnology (IEEE NANO 2008 2008), August 2008 , Texas, USA.

  • Efficient Model Order Reduction Technique using Subspace Iteration Scheme for Linear Time-Varying RLC Circuits, R Ravindra J V ,M.B Srinivas, 11th Euromicro Conference On Digital System Design Architectures, Methods and Tools (DSD 2008 2008), September 2008 , University of Parma, Parma, Italy. .

  • Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design, T Venkata Kalyan,Madhu Mutyam,P Vijaya Sankara Rao, 21st International Conference on VLSI Design, 2008 (VLSI Design 2008 2008), January 2008 :235-241 , Hyderabad, India.

  • Block remap with turnoff: A variation-tolerant cache design technique , Mohammed Abid Hussain,Madhu Mutyam, 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008 2008), January 2008 :783-788 , COEX, Seoul, Korea.

  • Read Stability and Write Ability Analysis of Dual-Vt Configurations of a single Cell of an SRAM Array-Effect of Process-Induced Intra-Die Vt Variations, Mamatha Samson,M.B Srinivas, 2nd IEEE International Nanoelectronics Conference (INEC 2008 2008), March 2008 :1015-1019 , Shanghai, China.

  • Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with In-Built Error Detection, Avinash Lingamneni,Kirthi Krishna Muntimadugu,M.B Srinivas, IEEE Computer Society Annual Symposium on VLSI, 2008 (ISVLSI 2008 2008), April 2008 , Montpellier, France.

  • Power management of variation aware chip multiprocessors. , Abu Saad Papa,Madhu Mutyam, ACM Great Lakes Symposium on VLSI 2008, May 2008 :423-428 , Orlando, Florida, USA.

  • Generic Sub-Space Algorithm for Generating Reduced Order Models of Linear Time Varying VLSI Circuits, R Ravindra J V ,M.B Srinivas, 18th ACM Great Lakes Symposium on VLSI (GLSVLSI-2008 2008), May 2008 :111-114 .

  • Generating Reduced Order Models for High Speed VLSI Interconnects using Balancing-Free Square Root Method, R Ravindra J V ,M.B Srinivas, 12th IEEE Workshop on Signal Propagation on Interconnects (SPI 2008 2008), May 2008 , Avignon, Popes Palace, France. (IEEE Computer Press).

  • Amplifying ZPPSAT[1] and the two queries problem, Richard Chang,Suresh Purini, 23rd Annual IEEE Conference on Computational Complexity (CCC 2008 2008), June 2008 , University of Maryland, College Park.

  • Word-interleaved cache: an energy efficient data cache architecture, T Venkata Kalyan,Madhu Mutyam, International Symposium on Low Power Electronics and Design 2008 (ISLPED 2008 2008), August 2008 :265-270 , National Science Seminar Complex, Indian Institute of Science, Bangalore, India .

  • Minimization of Energy Dissipation in Glitch free and Cascadable Adiabatic Logic Circuits, Reddy NSS,Satyam Mandavalli,K L Kishore, IEEE Region 10 Conference TENCON 2008 (TENCON 2008 2008), November 2008 :1-5 , Hyderabad, India.

  • A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder Subtractor, Sreehari Veeramachaneni,Kirthi Krishna Muntimadugu,G V Prateek,S Subroto,S Bharat,M.B Srinivas, 21st International Conference on VLSI Design, 2008 (VLSI Design 2008 2008), January 2008 :547-552 , Hyderabad, India.

  • Analyzing N-Curve Metrics for CMOS SRAM, Mamatha Samson,M.B Srinivas, 8th IEEE Conference on Nano technology, 2008 (IEEE NANO 2008 2008), August 2008.

  • Balancing coarse-grained pipelined architectures using multiple clock domains on platform FPGA, Sirisha Nalmela,Govindarajulu Regeti,Chidamber Kulkarni, IEEE High Performance Reconfigurable Computing Workshop, HiPC08, Bangalore http://www.hipc.org/hipc2008/ http://www.ewh.ieee.org/conf/hprcw/rcw08_tprogram.pdf http://www.hipc.org/hipc2008/documents/hipc2008-workshops-dec9.pdf, December 2008.

2007


  • A Low- Power, High Speed, Asynchronous VLSI Architecture for FIR Filters , R Ravindra J V ,Sandeep Saini,M.B Srinivas, 13th IEEE International Symposium Integrated Circuits (ISIC 2007 2007), September 2007 , Singapore.

  • Modeling and Analysis of Crosstalk for Distributed RLC Interconnects using Difference Model Approach, R Ravindra J V ,M.B Srinivas, ACM SIGDA 20th Symposium on Integrated Circuits and System Design (SBCCI 2007 2007), September 2007 :207-211 , Copacabana, Rio de Janeiro, Brazil..

  • Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs , R Ravindra J V ,M.B Srinivas, 2nd International Conference on Nano-Networks (Nano-Net 2007 2007), September 2007 , Catania, Italy.

  • Bus Coding to Minimize Redundant Bit Transitions, K S Sainarayanan,C Raghunandan,R Ravindra J V ,M.B Srinivas, IEEE Region 10 TENCON 2007 (TENCON 2007 2007), October 2007 , Taipei International Convention Center, Taipei, Taiwan.

  • Model Order Reduction for RLC Interconnects using Response Dependent Condensation, R Ravindra J V ,M.B Srinivas, IEEE Region 10 TENCON 2007 (TENCON 2007 2007), October 2007 , Taipei International Convention Center, Taipei, Taiwan .

  • Technique for Minimizing Power Consumption in Array Multipliers through Input Vector Ordering, N Vasantha,Satyam Mandavalli,K Subba Rao, International Conference on Signal Processing, Networking and Communications 2007 (IEEE-ICSCN-2007 2007), February 2007 :162-167 , MIT Campus, Anna University, Chennai, India.

  • Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme, K S Sainarayanan,C Raghunandan,M.B Srinivas, IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2007 2007), May 2007 :401 , Porto Alegre, Brazil .

  • Impact of Process Variations on Bus-Encoding Schemes for Delay Minimization in VLSI Interconnects, C Raghunandan,K S Sainarayanan,M.B Srinivas, 11th IEEE Workshop on Signal Propagation on Interconnects (SPI-2007 2007), May 2007 , Ruta di Camogli (Genova), Italy.

  • Analytical Crosstalk Model with Inductive Coupling in VLSI Interconnects, R Ravindra J V ,M.B Srinivas, 11th IEEE Workshop on Signal Propagation on Interconnects (SPI-2007) (SPI-2007 2007), May 2007 , Ruta di Camogli (Genova), Italy.

  • Novel High-Speed Redundant Binary to Binary Converter Using Prefix Networks, Sreehari Veeramachaneni,Kirthi Krishna Muntimadugu,Avinash Lingamneni,P Sreekanth Reddy,M.B Srinivas, IEEE International Symposium on Circuits and Systems (ISCAS-2007 2007), May 2007 , New Orleans, USA.

  • Bounded queries and the NP machine hypothesis, Richard Chang,Suresh Purini, 22nd Annual IEEE Conference on Computational Complexity, June 2007 :52-59 , San Diego, California, USA.

  • A Comparative Study of Different FFT Architectures for Software Defined Radio, Shashank Mittal,Md Zafar Ali Khan,M.B Srinivas, International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS-Workshop VII 2007), July 2007 , Samos, Greece.

  • Coupling Aware Energy-Efficient Data Scrambling On Memory-Processor Interfaces, K S Sainarayanan,R Ravindra J V ,C Raghunandan,M.B Srinivas, 2nd IEEE International Conference on Industrial and Information Systems (ICIIS 2007 2007), August 2007 , University of Peradeniya, Srilanka..

  • A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects, R Ravindra J V ,M.B Srinivas, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007 2007), August 2007 .

  • Response Dependent Condensation Based Macromodeling for Linear Time Varying High Speed VLSI Interconnects, R Ravindra J V ,M.B Srinivas, 7th International Symposium on Communications and Information Technologies (ISCIT 2007 2007), October 2007.

  • Modeling of Full-Wave High Speed On Chip RLC Interconnects using Frequency Shift Technique, R Ravindra J V ,M.B Srinivas, 9th IEEE Electronics Packaging Technology Conference (EPTC 2007 2007), December 2007 .

2006


  • A Novel Low Power Bus Encoding Technique for Minimizing RGB Transitions for LCD Display of Digital Camera, R Ravindra J V ,K S Sainarayanan,M.B Srinivas, 10th IEEE VLSI Design and Test Symposium 2006 (VDAT-2006 2006), August 2006 , International Centre, Dona Paula, Goa.

  • Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method , K S Sainarayanan,R Ravindra J V ,M.B Srinivas, 3rd International Workshop on Electronic Design, Test and Applications (DELTA-2006 2006), January 2006 , Kuala Lumpur, Malaysia.

  • A Low Power Overhead Bus Coding Technique for Minimizing Inductive Crosstalk in VLSI Interconnects, K S Sainarayanan,R Ravindra J V ,M.B Srinivas, The 15th International Workshop on Logic & Synthesis (IWLS 2006 2006), June 2006 , Vail, Colorado, USA..

  • Crosstalk Aware Low Power Bus Coding for VLSI Interconnects, K S Sainarayanan,R Ravindra J V ,Kiran T Nath,M.B Srinivas, IEEE-North East Workshop on Circuit and Systems 2006 (NEWCAS 2006 2006), June 2006 , Holiday Inn Gatineau, QC, Canada.

  • Efficient Spatial-Temporal Coding Schemes for Minimizing Delay in Interconnects, K S Sainarayanan,C Raghunandan,R Ravindra J V ,M.B Srinivas, IEEE Region 10 Conference TENCON 2006 (IEEE TENCON 2006 2006), November 2006 , Hong Kong.

  • Coding for Minimizing Energy in VLSI Interconnects, K S Sainarayanan,R Ravindra J V ,Kiran T Nath,M.B Srinivas, 18th International Conference on Microelectronics ((ICM) 2006 2006), December 2006 , King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia.

  • Delay and Energy Efficient Spatial Coding Technique for Low Power VLSI Applications, R Ravindra J V ,M.B Srinivas, 6th International Workshop System-on-Chip for Real-Time Applications (IWSOC-2006 2006), December 2006 , Cairo, Egypt.

  • A Novel, Coupling Driven, Low Power Bus Coding Technique for Minimizing capacitive Crosstalk in VLSI Interconnects, K S Sainarayanan,R Ravindra J V ,M.B Srinivas, IEEE International Symposium on Circuits and Systems (ISCAS-2006 2006), May 2006 .

  • Delay and peak power minimization for on-chip buses using temporal redundancy, K Najeeb,Vishal Gupta,Madhu Mutyam,V Kamakoti, 16th ACM Great Lakes Symposium on VLSI (GLSVLSI'06), Philadelphia, April 30 - May 2, 2006, November 2006 .

  • Working with process variation aware caches, Madhu Mutyam,Vijaykrishnan Narayanan, nternational Conference on Design Automation and Test in Europe (DATE'07), April 16-20, 2007, Acropolis, Nice, France, November 2006 .

  • Delay and Energy Efficient Data Transmission for On-Chip Buses, Madhu Mutyam,Melvin Eze,N Vijaykrishnan,Yuan Xie, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), January 2006 .

2005


  • A Novel Bus Coding Technique for Low Power Data Transmission, R Ravindra J V ,K S Sainarayanan,M.B Srinivas, 9th IEEE VLSI Design and Test Symposium 2005 (VDAT-2005 2005), August 2005 :263-266 , Bangalore, Karnataka.

  • An Efficient Power Reduction Technique for Low Power Data I/O Using Gray Code, K S Sainarayanan,R Ravindra J V ,M.B Srinivas, IEEE International Conference on Applied Electronics , September 2005 :283-286 , Univ. of West Bohemia, Pilsen, Czech Republic.

  • EDGE: Encoding and Decoding of Generic Data for Minimizing Switched Capacitance and Transition Density for Low Power VLSI Applications, R Ravindra J V ,K S Sainarayanan,M.B Srinivas, IEEE International Conference on SOC (ISOCC 2005 2005), October 2005 , Seoul, Korea.

  • A Novel Deep Sub-Micron Low Power Bus Coding Technique, K S Sainarayanan,R Ravindra J V ,M.B Srinivas, In Proc. of International Association of Science and Technology for Development [Circuits, Signals, And Systems (CSS 2005)] (IASTED [CSS 2005] 2005), October 2005 , Marina Del Rey, USA [/ http://www.actapress.com/Abstract.aspx?paperId=22130].

  • An Efficient Power Reduction Technique for Low Power Data I/O for Military Applications , R Ravindra J V ,K S Sainarayanan,M.B Srinivas, 24th Digital Avionics Systems Conference (DASC 2004 2005), October 2005 , Hyatt Regency Crystal City, Washington, D.C..

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