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Center for VLSI and Embedded System Technologies

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FACULTY PROFILE

DR. ZIA ABBAS
Assistant Professor
Ph.D. Sapienza University of Rome, Italy

Research Interest

Low power VLSI design, Statistical variations aware modeling and optimization of CMOS and FinFET circuits, High yield designs, Reliability issues in nanoscale CMOS and FinFET circuits, Current-mode circuits.

Selected Publications
  • Abbas, Zia, Mauro Olivieri, and Andreas Ripp, "Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations," Journal of Computational Electronics, vol. 15, no. 4, pp. 1424-1439, 2016.
  • Abbas, Zia, and Mauro Olivieri, "Optimal transistor sizing for maximum yield in variation-aware standard cell design," International Journal of Circuit Theory and Applications 44 (2015): 1400-1424.
  • Prateek Gupta, Shirisha Gourishetty, Harshini Mandadapu, Zia Abbas, “PVT Variations Aware Robust Transistor Sizing forPower-Delay Optimal CMOS Digital Circuit Design”, IEEE International Symposium on Circuits and Systems (ISCAS),2019
  • Prateek Gupta, Harshini Mandadapu, Shirisha Gourishetty, Zia Abbas, “Robust Transistor Sizing for Improved performance in Digital Circuits using Optimization Algorithms” 20th International Symposium on Quality Electronic Design (ISQED), 2019
  • Prateek Gupta, Shubham Kumar, Zia Abbas, “Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power.” 88-99, VDAT 2018
  • Prateek Gupta, Shirisha Gourishetty, Harshini Mandadapu, Zia Abbas, “PVT Variations Aware Robust Transistor Sizing forPower-Delay Optimal CMOS Digital Circuit Design”, IEEE International Symposium on Circuits and Systems (ISCAS),2019
  • Prateek Gupta, Harshini Mandadapu, Shirisha Gourishetty, Zia Abbas, “Robust Transistor Sizing for Improved performance in Digital Circuits using Optimization Algorithms” 20th International Symposium on Quality Electronic Design (ISQED), 2019
  • Prateek Gupta, Harshini Mandadapu, Shirisha Gourishetty, Zia Abbas, “Robust Transistor Sizing for Improved performance in Digital Circuits using Optimization Algorithms” 20th International Symposium on Quality Electronic Design (ISQED), 2019
  • Prateek Gupta, Shirisha Gourishetty, Harshini Mandadapu, Zia Abbas, “PVT Variations Aware Robust Transistor Sizing forPower-Delay Optimal CMOS Digital Circuit Design”, IEEE International Symposium on Circuits and Systems (ISCAS),2019
  • Ashfakh Ali, Saikiran Lade, Arpan Jain and Zia Abbas, "A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications" Very Large Scale Integration (VLSI-SoC) 2019
  • Arpan Jain, Ashfakh Ali, Saikiran Lade and Zia Abbas "A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications" IEEE International Symposium on Circuits and Systems (ISCAS), 2019
  • Arpan Jain, Ashfakh Ali, Saikiran Lade and Zia Abbas "A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications" IEEE International Symposium on Circuits and Systems (ISCAS), 2019
  • Ashfakh Ali, Saikiran Lade, Arpan Jain and Zia Abbas, "A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications" Very Large Scale Integration (VLSI-SoC) 2019
  • Ashfakh Ali, Arpan Jain and Zia Abbas "Voltage Level Adapter for High Swing Applications in CMOS Differential Amplifiers" 2018 VLSI Design and Test (VDAT) 2018
  • H. Nayeem, A. Syed and Md. Zafar Ali Khan, “Low Cost Wavelength Specific Water Quality Measurement Technique” in 2019 41st Ann. Int. Conf. of the IEEE Engg. in Med. and Bio. soc. (EMBC), IEEE, 2019
  • Ashfakh Ali, Arpan Jain and Zia Abbas "Voltage Level Adapter for High Swing Applications in CMOS Differential Amplifiers" 2018 VLSI Design and Test (VDAT) 2018
  • Ashfakh Ali, Saikiran Lade, Arpan Jain and Zia Abbas, "A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications" Very Large Scale Integration (VLSI-SoC) 2019
  • Arpan Jain, Ashfakh Ali, Saikiran Lade and Zia Abbas "A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications" IEEE International Symposium on Circuits and Systems (ISCAS), 2019

Education Profile
  • Ph.D. from Sapienza University of Rome, Italy in 2014.
  • MS from Kanpur University, India in 2001.
  • M Tech Gold Medalist from Integral University, Lucknow, Uttar Pradesh India in 2000.

Professional Profile
  • Assistant Professor , IIIT Hyderabad Present
  • Post-Doctoral Researcher Sapienza University, Rome till 2016
  • Researcher MunEDAGmbH, Munich Germany till 2012
  • Senior Lecturer Amity University , Lucknow Campus till 2010
  • Lecturer Integral University, Lucknow, Uttar Pradesh

Scientific and Professional Memberships
  • NA.

Awards
  • Winner (Rank -1) of International fellowship for PhD , Sapienza University, Rome in 2010, Winner of Marie-Curie Actions Fellowship for Industry Academia Partnership and Pathways (IAPP) Framework Program 7, collaboration for continuous coordination in 2011.

IIIT-H Affiliations
  • NA.


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