Harshini

dd Student
Research Advisor: Dr. Zia Abbas
Co-Advisor:

IIIT-H Email: h.mandadapu@students.iiit.ac.in
Linkedin Profile: https://www.linkedin.com/in/harshini-chowdary-b2b488142/



Research Area

Research on Low Power and High Performance in VLSI ; Used optimization algorithms such as Least Square, Particle Swarm Optimization (PSO), Simulated annealing, Averaging with ABC(normal), Genetic Algorithm and Artificial Bee Colony (ABC), for sizing transistors to reduce leakages and delays, maintaining area.Also worked on, A high throughput FPGA based Floating Point Conjugate Gradient Implementation.

Selected Publications
  • Prateek Gupta, Shirisha Gourishetty, Harshini Mandadapu, Zia Abbas, “PVT Variations Aware Robust Transistor Sizing forPower-Delay Optimal CMOS Digital Circuit Design”, IEEE International Symposium on Circuits and Systems (ISCAS),2019
  • Prateek Gupta, Harshini Mandadapu, Shirisha Gourishetty, Zia Abbas, “Robust Transistor Sizing for Improved performance in Digital Circuits using Optimization Algorithms” 20th International Symposium on Quality Electronic Design (ISQED), 2019

Education Profile
  • B. Tech from International Institute of Information Technology, Hyderabad.

Professional Profile

Software and Hardware Experience
HSPICE, Cadence, Python, Verilog, Xilinx, FPGA.

Projects
Robust Transistor Sizing for Improved Performances in Digital Circuits Using Optimization Algorithms, Implementation of BIST in Design for Te-stability, Design and Implementation of Power Efficient Booth Multiplier on FPGA in VLSI Architecture, Rotating LED Clock in EW-2