Prasenjit Saha

ms Student
Research Advisor: Dr. Zia Abbas
Co-Advisor:

IIIT-H Email: prasenjit.saha@research.iiit.ac.in
Linkedin Profile: https://www.linkedin.com/in/prasenjit-saha-8827a1179/



Research Area

Modifying a given netlist in terms of transistor sizing in order to reduce the leakages and delays for the given circuit. While sizing the transistors, Process Variations, Temperature variations and Supply Voltage variations have been taken into consideration. The process includes application of mathematical optimization to the design of standard cells that are robust to process variations in all the operating conditions.

Selected Publications

Education Profile
  • B. Tech from Heritage Institute of Technology, Kolkata.

Professional Profile
  • Worked as SAP consultant in Infosys ltd, Bangalore, 2 years.

Software and Hardware Experience
Cadence, HSPICE, Python

Projects
Design of High-Gain Op amp , Key-Value Store Architecture for fast computation using FPGA