S Harsha Keerthan

dd Student
Research Advisor: Dr. Azeemuddin Syed
Co-Advisor: Dr. Shaik Qadeer, Dr. Zafar Ali Khan

IIIT-H Email: sharsha.keerthan@research.iiit.ac.in
Linkedin Profile: www.linkedin.com/in/harsha-keerthan-4b8614112



Research Area

My research work is on the efficient VLSI implementation of the Fast Fourier Transform algorithms. Tangent FFT algorithms have very low arithmetic complexities and that can be used for efficient VLSI implementations of FFT cores. Even though the Tangent FFT algorithms have very low arithmetic complexities their implementations are very less explored. Choosing an appropriate hardware is important to get the advantage of the low arithmetic complexities of Tangent FFT's during implementation.

Selected Publications
  • Harsha Keerthan, Shaik Qadeer, Syed Azeemuddin, and Zafar Ali Khan. "Parallel and Pipelined VLSI Implementation of the new radix-2 DIT FFT algorithm" Smart Electronic Systems (iSES), 2018 IEEE International Symposium on. IEEE, 2018.

Education Profile
  • B. Tech from International Institute of Information Technology, Hyderabad.

Professional Profile
  • Worked as Assistant Professor in , IIIT HyderabadPresent.
  • Worked as Post-Doctoral Researcher in Sapienza University, Rome till 2016.
  • Worked as Researcher in MunEDAGmbH, Munich Germany till 2012.
  • Worked as Senior Lecturer in Amity University , Lucknow Campus till2010.
  • Worked as Lecturer in Integral University, Lucknow, Uttar Pradesh.

Software and Hardware Experience
Cadence RTL Compiler (RC Encounter), Xilinx Vivado, Modelsim Verilog, Matlab, VHDL Hardware: Arduino, FPGA

Projects
Built in Self Test in Design for Te-stability, Modified Radix-2 FFT Implementation using optimal CSD Complex Constant Multipliers, DFT Implementation using 2-D Systolic Array, Low Noise Amplifier in CMOS RFIC, QR Decomposition Core with Partial Reconfiguration in VLSI Architecture